Hardware Synthesis of A Parallel JPEG Decoder from Its Functional Specification

Hawkins, John and Abdallah, Ali E. (2004) Hardware Synthesis of A Parallel JPEG Decoder from Its Functional Specification. In: Design Methods and Applications for Distributed Embedded Systems. Springer, Boston, MA, pp. 197-206. ISBN 978-1-4020-8148-4

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Abstract

Recent advances in manufacturing programmable logic devices, such as the FPGA, have made it possible to obtain reconfigurable circuits with upwards of one hundred million gates. Although we have such enormously powerful hardware at our fingertips, we are still somewhat lacking in techniques to properly exploit this technology to its full potential. In previous work, we have proposed a development methodology based on transformational programming and process refinement for producing provably correct solutions. Starting with a clear, intuitively correct specification of the problem, in a functional language such as Haskell, we apply a set of formal transformation laws to refine it into a behavioural definition in Handel-C, exposing the implicit parallelism along the way. This definition can then be compiled onto an FPGA. We apply this technique to a non-trivial, real world problem - a JPEG decompression algorithm, and achieve a truly scalable, parallel hardware implementation.

Item Type: Book Section
Subjects: G400 Computer Science
Divisions: Faculty of Computing, Engineering and the Built Environment
Faculty of Computing, Engineering and the Built Environment > School of Computing and Digital Technology
Faculty of Computing, Engineering and the Built Environment > School of Computing and Digital Technology > Cyber Security
UoA Collections > UoA11: Computer Science and Informatics
Depositing User: Oana-Andreea Dumitrascu
Date Deposited: 07 Apr 2017 11:27
Last Modified: 07 Apr 2017 11:27
URI: http://www.open-access.bcu.ac.uk/id/eprint/4235

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